Low-Power ECG-Based Processor for Predicting Ventricular
Arrhythmia
ABSTRACT:
This paper presents the
design of a fully integrated electrocardiogram (ECG) signal processor (ESP) for
the prediction of ventricular arrhythmia using a unique set of ECG features and
a naive Bayes classifier. Real-time and adaptive techniques for the detection
and the delineation of the P-QRS-T waves were investigated to extract the
fiducial points. Those techniques are robust to any variations in the ECG
signal with high sensitivity and precision. Two databases of the heart signal
recordings from the MIT PhysioNet and the American Heart Association were used
as a validation set to evaluate the performance of the processor. Based on
application-specified integrated circuit (ASIC) simulation results, the overall
classification accuracy was found to be 86% on the out-of-sample validation
data with 3-s window size. The
proposed architecture of this paper analysis the logic size, area and power
consumption using Xilinx 14.2.
EXISTING SYSTEM:
Recently, due to the
remarkable advancement in technology, the development of dedicated hardware for
accurate ECG analysis and classification in real time has become possible. The
main requirements are low-power consumption and low-energy operation in order
to have longer battery lifetime along with the small area for wearability. Many
attempts succeeded to implement ECG signal processing and classification
systems in hardware. Shiu et al. implemented an integrated electrocardiogram
signal processor (ESP) for the identification of heart diseases using the 90-nm
CMOS technology. The system employed an instrumentation amplifier and a
low-pass filter (LPF) to remove the baseline wander and the power line
interference form the ECG and employed a time-domain morphological analysis for
the feature extraction and classification based on the evaluation of the ST
segment. The system was carried out in a field programmable gate array and
consumed a total of 40.3-μW power and achieved an accuracy of 96.6%. The main
disadvantage of the system is that it uses fixed search window with predefined
size to locate S and T fiducial points, which is not suitable for real-time
scenarios.
The system was fabricated
on the 0.18-μm CMOS technology and executed different functions for the three
stages of preprocessing, feature extraction, and classification. The algorithm
behind these functions was based on the quad level vector. Moreover, the
functions were all pipelined to increase hardware utilization and reduce power
consumption. Besides, the system employed clock gating techniques to enable and
disable each processing unit individually according to the need and it applied
voltage scaling up to 0.7 V. The ECG processor consumed 6 μW at 1.8 V and 1.26
μW at 0.7 V, which is much better than the system due to the low-power
techniques it employed. One recent system for ECG classification was presented
and comprised of three chips. The first chip contained the body-end circuits
that were the high-pass sigma delta modulator-based bio-signal processor and
the ON–OFF keying transmitter. The second chip, the receiving end, had the
receiver and the digital signal processing (DSP) unit. The last chip was the
classifier. Discrete wavelet transform was adopted by the DSP unit for the ECG
feature extraction and classification. The chip was fabricated on the 0.18-μm CMOS
technology and consumed a total power of 5.967 μW at 1.2 V for the DSP unit
only. The accuracy of the beat detection and the ECG classification was 99.44%
and 97.25%, respectively.
DISADVANTAGES:
·
large
area
·
high
power
·
high
performance
PROPOSED SYSTEM:
The architecture of the
proposed ESP is shown in Fig. 1. The architecture includes the modules of the
three stages along with a main FSM that controls the flow of the data between
the different stages, as shown in Fig. 2. The processing of the data is done
using fixed point representation.
Fig. 1. Architecture of the proposed ESP.
Fig. 2. Main control FSM.
ECG Preprocessing Stage
1) ECG Filtering: The
block diagram of the preprocessing stage is shown in Fig. 3. Bandpass filtering
of the raw ECG signal is the first step in which the filter isolates the
predominant QRS energy centered at 10 Hz, and attenuates the low frequencies
characteristic of the P and T waves, baseline drift, and higher frequencies
associated with electromyographic noise and power line interference.
Fig. 3. Block diagram of preprocessing stage, which contains filtering,
QRS detection, and P and T wave delineation.
2) QRS Detection: To
detect the QRS complex, the PAT method was used. The PAT is a widely used
method, which is based on the amplitude threshold technique exploiting the fact
that R peaks have higher amplitudes compared with other ECG wave peaks. With
proper filtering of the signal, the method is highly capable of detecting the R
peaks in every heartbeat using two threshold levels.
Fig. 4. Flowchart of PAT peak detection technique.
3) T and P Wave
Delineation: The delineation of T and P waves is based on a novel technique
proposed. The method is based on adaptive search windows along with adaptive
thresholds to accurately distinguish T and P peaks from noise peak. In each
heartbeat, the QRS complex is used as a reference for the detection of T and P
waves in which two regions are demarcated with respect to R peaks.
Fig. 5. Computing T and P wave thresholds based on the previously
detected T peak, P peak, and R peak values.
Feature Extraction Stage
The two main parameters
that must be considered while developing a detection (or prediction) system are
the complexity and the accuracy of the feature extraction technique in
providing the best results. The result of such analysis yielded in a unique set
of ECG features, which were found to be the most indicative characteristics of
ventricular arrhythmia with a simple-torealize system and high prediction
accuracy. The features include RR, PQ, QP, RT, TR, PS, and SP intervals. Fig. 6
shows these intervals on ECG record. It is worth mentioning that the features
are extracted from two consecutive heartbeats, unlike other methods that
process each heartbeat independently.
Fig. 6. ECG feature extraction from two consecutive heartbeats.
Classification Stage
The choice of classifier
in this paper was the naive Bayes. The naive Bayes classifier is easy to build
with no complicated iterative parameter estimation, which makes it particularly
useful for hardware implementation. It assumes naive and strong independent
distributions between the feature vectors, and this assumption was met, since
all the extracted ECG features were independently analyzed and assessed from
the beginning. The architecture of the classifier is implemented, as shown in
Fig. 7.
Fig. 7. Architecture of naive Bayes classifier.
ADVANTAGES:
·
small
area
·
low
power
·
high
performance
SOFTWARE
IMPLEMENTATION:
·
Modelsim
·
Xilinx ISE
