A New Parallel VLSI Architecture for Real-time Electrical
Capacitance Tomography
ABSTRACT:
This paper presents a
fixed-point reconfigurable parallel VLSI hardware architecture for real-time
Electrical Capacitance Tomography (ECT). Another FPGA module performs the
inverse steps of the tomography algorithm. A dual port built-in memory banks
store the sensitivity matrix, the actual value of the capacitances, and the
actual image. A two dimensional (2D) core multiprocessing elements (PE) engine
intercommunicates with these memory banks via parallel buses. We are focus only
on the FPGA module because the design is decide the power consumption and cost.
The proposed architecture of this paper analysis the logic size, area and power
consumption using Xilinx 14.2.
ENHANCEMENT OF THE PROJECT:
Use color image for the
processing .i.e., RGB image.
EXISTING
SYSTEM:
Electrical Capacitance
Tomography (ECT) is an effective technique to measure a process non-intrusively
by reconstructing the 2D or 3D dielectric distribution of its different
constituencies. This makes ECT a good candidate for several industrial
applications such as two-phase flow monitoring, quality control in
manufacturing industry, and corrosion detection. In the last few years, several
ECT systems have already been suggested.
Most of them used a
desktop computer as a main processing unit and focused their research mainly on
improving the accuracy and execution time of the algorithms on general purpose
computers. Nevertheless, the tremendous computation complexity of the
tomography algorithms let them to be executed still relatively slowly (in few
seconds order), preventing them to sustain real-time applications. Hence, only
few research works have been done on designing dedicated hardware architectures
for ECT tomography using either DSP processor or FPGA technology. In, a
dedicated architecture based on the DSP processor, TMS320C6701; operating at
133 MHz was suggested for the image reconstruction algorithm. The system
consists of 12 electrodes and claimed to be able to achieve the image
reconstruction of images of 480 pixels within a throughput of 135 frames/s,
when using the Linear Back Project (LBP) algorithm. Similarly, in a TMS3206416
processor was used in LBP-based ECT system with 16 electrodes to achieve a
throughput of 200 frames/s.
Other works were also
suggested for FPGA-based image reconstruction targeting other tomography
modalities such as computed tomography (CT) and Single-Photon Emission Computed
Tomography (SPECT).FPGA-based Electrical Impendence Tomography (EIT) system
comprises several FPGA-based Impedance Measurement Modules (IMM) comprising
independent current sources and voltmeters intercommunicating through a
reconfigurable FPGA-based Intra-network controller.
DISADVANTAGES:
·
It’s
only for gray scale based process
·
Performance
is less
PROPOSED SYSTEM:
This constitutes the core engine of our ECT
system since it performs the image reconstruction task for color images (i.e.
RGB format images). Figure 4 shows the derailed VLSI architecture. It is
modular and divided into four main modules,
1. A parallel processing module
2. A data variable input/output memories modules
3. A sequencer and memory controller modules
4. Post processing modules
We are only focus on processing unit for this
proposed system with RGB format image processing. The parallel processing
module is parallel like architecture which is composed of several similar
adder/multiplier processing units. Each of these units is scalable and consists
of three pipelined stages: Decomposition stages, Basic unit operation stages,
Composition stages. Figure shows these stages at both matrix and bit-levels.
For the three afro-mentioned algorithms, the
matrix decomposition consists to divide the two matrices to multiply into
regular square blocks (q * q) which are then simultaneously processed by the
parallel processing units using bit decomposition techniques.
The basic unit operator stage in matrix level
covers decomposition stage in bit level, basic unit operation stages in bit
level; add composition stage in bit level as described in below. Figure 6 shows
the overall operations in basic unit operation stage. Port A and port B are the
input ports of the k-processing unit.
Figure 6: Overall architecture with three main units. Figure is illustrated with
the number of basic operators, N basic, which equal to 4.
ADVANTAGES:
•
Increase the
performance
SOFTWARE
IMPLEMENTATION:
·
Modelsim
·
Xilinx ISE
