A Fully Digital Front-End Architecture for ECG Acquisition
System with 0.5 V Supply
ABSTRACT:
This
paper presents a new power-efficient electrocardiogram acquisition system that
uses a fully digital architecture to reduce the power consumption and chip area.
The proposed architecture is compatible with digital CMOS technology and is
capable of operating with a low supply voltage of 0.5 V. In this architecture,
no analog block, e.g., low-noise amplifier (LNA), and filters, and no passive
elements, such as ac coupling capacitors, are used. A moving average voltage-to
time converter is used, which behaves instead of the LNA and anti-aliasing
filter. A digital feedback loop is employed to cancel the impact of the dc
offset on the circuit, which eliminates the need for coupling capacitors. The
proposed architecture of this paper analysis the logic size, area and power
consumption using Xilinx 14.2.
EXISTING SYSTEM:
A
digital signal processor then processes the digital data for monitoring or
diagnosis applications. Biomedical signal acquisition systems typically consist
of a low-noise amplifier (LNA), a bandpass filter, an analog sample-and-hold,
and an analog-to-digital converter (ADC), as shown in Fig. 1(a). While the
architecture shown in Fig. 1(a) is typically used, in some cases chopping
technique is used to reduce the impact of the flicker noise, as shown in Fig.
1(b).
Fig. 1. Biomedical signal
acquisition system. (a) Conventional based. (b) Chopper based.
With
the advancement of CMOS technology, the supply voltage is being reduced, which
decreases the voltage headroom for analog block of an IC. Although the
technology scaling leads to lower power consumption and higher performance in
digital circuits; many parameters [such as signal-to-noise ratio (SNR), dynamic
range, gain, and so on] of the analog parts of an IC are negatively impacted.
Therefore, it is desirable to find new architectures, in which more digital
blocks are used. Recently, a few methods, which are based on digital
techniques, are introduced. The block diagram of the system designed is shown
in Fig. 2. In this circuit, many of the functions that are typically
implemented by analog blocks are performed by digital circuits. Using this
digitally enhanced approach can help increase the flexibility of the system in
removing unwanted interferences. Moreover, digital calibration techniques can
be used more easily.
Fig. 1. Biomedical signal
acquisition system. (a) Conventional based. (b) Chopper based.
Disadvantages:
·
Power consumption is high
·
Coverage area is high
PROPOSED SYSTEM:
Fig.
3(a) shows the block diagram of the proposed fully digital architecture. In
this structure, the processing of the bio-signal is performed in the time and
digital domain. Hence, the advantages of digital CMOS technology are utilized.
The analog bio-signal coming from the electrode is directly connected to the
front-end circuit and is converted to time with a voltage-to-time converter
(VTC). From this point on in the circuit, the signal information is in the
phase of the VTC output signal. The output of the VTC is applied to the
time-mode processing block, in which the anti-aliasing and offset cancellation
are done in time domain. Then, a time-to-digital converter (TDC) transfers the
time-mode signal into digital domain where other processes (digital filtering,
data compression/reduction and so on) are performed.
The
proposed digital architecture is shown in Fig. 3(b). It consists of an active
electrode, two digital-to-current converters (DCCs), a moving average VTC
(MA-VTC), a control logic block, a counter, and a demultiplexer. In this
architecture, ac coupling capacitors are removed, and the impact of the
electrode offset on the circuit is cancelled via a feedback loop. The technique
used for the offset cancellation will be described in Section III. As explained
earlier (Fig. 1), in conventional bio-signal acquisition systems, an LNA is
used after the electrode. In the proposed architecture, this block is removed.
In the following text, each of the blocks of the proposed architecture is
explained.
Fig. 3. (a) Overall block diagram
of the proposed system. (b) Proposed digital front-end architecture.
Active
Electrode
An
active electrode is an electrode, in which some active elements are used to
reduce the power line interference. Fig. 4 shows two different two-wired active
electrodes for comparison.
Fig. 4. Active electrode with
either (a) an op-amp or (b) a MOS transistor, both operating as a voltage
follower
Voltage
to Time Converter (VTC)
In
the proposed digital implementation, the analog input voltage is converted to a
measurable time via a VTC at the first stage. The signal information is now in
the delay of the clock signal (CLK).
Moving
Average Filtering
Since,
VTCs work with a clock and are broadband compared with the signal bandwidth,
not using an anti-aliasing filter before VTCs would lead to out-of-band noise
aliasing. To prevent aliasing and to avoid having an analog filter in the
design, we have developed the structure shown in Fig. 5 for converting the
voltage-to-time as well as anti-aliasing filtering.
Fig. 6. Schematic of the MA-VTC
circuit.
Architecture
for offset cancellation technique
The
block diagram of the proposed offset cancellation technique is shown in Fig. 6.
It contains two 5-bit DCCs, control logic circuit, 5-bit counter, and 5–32
demultiplexer (Demux). Since the offset voltage changes very slowly, the
frequency of the clock signal used for the counter (Clkc) is ∼10 times less than the
clock of the rest of the circuit.
Fig. 10. Proposed offset
cancellation block diagram.
Advantages:
·
Compact
·
Low power consumption
Software
implementation:
·
Modelsim
·
Xilinx ISE
