Load-Balancing Multipath Switching System with Flow Slice

ABSTRACT:
Multipath Switching systems (MPS) are intensely used in state-of-the-art core routers to provide terabit or even petabit switching capacity. One of the most intractable issues in designing MPS is how to load balance traffic across its multiple paths while not disturbing the intraflow packet orders. Previous packet-based solutions either suffer from delay penalties or lead to OðN2Þ hardware complexity, hence do not scale. Flow-based hashing algorithms also perform badly due to the heavy-tailed flow-size distribution. In this paper, we develop a novel scheme, namely, Flow Slice (FS) that cuts off each flow into flow slices at every intraflow interval larger than a slicing threshold and balances the load on a finer granularity. Based on the studies of tens of real Internet traces, we show that setting a slicing threshold of 1 _4 ms, the FS scheme achieves comparative load-balancing performance to the optimal one. It also limits the probability of out-of-order packets to a negligible level (10_6) on three popular MPSes at the cost of little hardware complexity and an internal speedup up to two. These results are proven by theoretical analyses and also validated through trace-driven prototype simulations.


 ARCHITECTURE:

       
                                  
EXISTING SYSTEM
Our major improvement over the existing works is to tailor the approach in the scenario by introducing the offline delay bound calculation, while the previous solutions either use an empirical slicing threshold or maintain flow context to facilitate the slicing. The traces here are collected at backbone links of one of the largest commercial backbones worldwide.

DISADVANTAGE OF EXISTING SYSTEM:
Ø Our major improvement over the existing works is to tailor the FS approach in the MPS scenario by introducing the offline delay bound.

PROPOSED SYSTEM:
In this project a novel load-balancing scheme, namely, Flow Slice, based on the fact that the intraflow packet interval is often, larger than the. Due to three positive properties of flow slice, our scheme achieves good load-balancing uniformity with little hardware overhead and timing complexity. By calculating delay bounds at three popular, we show that when the slicing threshold is set to the smallest admissible value at, the FS scheme can achieve optimal performance while keeping the intraflow packet out-of-order probability negligible given an internal speedup up to two. Our results are also validated through trace-driven prototype simulations under traffic patterns.

ADVANTAGE OF PROPOSED SYSTEM:

Ø It is immune to packet loss, while other solutions like the  resequencer require additional loss detection Mechanisms.

MODULES:
        
1.    Load-balancing scheme,
2.    Multipath switching system,
3.    Multistage multiplane clos switches,






MODULES DESCRIPTION:

Load-Balancing Scheme:
              Interflow packet order is natively preserved besetting slicing threshold to the delay upper bound at .Any two packets in the same flow slice cannot be disordered as they are dispatched to the same switching path where  processing is guaranteed; and two packets in the same flow but different flow slices will be in order at departure, as the earlier packet will have depart from before the latter packet arrives. Due to the fewer number of active flow slices, the only additional overhead in, the hash table, can be kept rather small, , and placed on-chip to provide ultrafast access speed. This table size depends only on system line rate and will stay unchanged even if scales to more than thousand external ports, thus guarantees system scalability.

MULTIPATH SWITCHING SYST:
          Through lay-aside Buffer Management module, all packets are virtually queued at the output according to the flow group and the priority class in a hierarchical manner. The output scheduler fetches packets to the output line using information provided by. Packets in the same flow will bevirtually buffered in the same queue and scheduled in discipline. Hence, intraflow packet departure orders holdas their arriving orders at the multiplexer. Central-stage parallel switches adopt an output-queued model. By Theorem, we derive packet delay bound at firststage. We then study delay at second-stage switches. Define native packet delay at stage m of an be delay experienced at stage m on the condition that all the preceding stages immediately send all arrival packets out without delay.


Multistage Multiplane Clos Switches :

We consider the Multistage Multiplane Clos-networkbased switch by Chao et a . It is constructed of five stages of switchmodules with top-level architecture similar to a external input/output ports. The first and last stages Clos are composed of  input demultiplexers and output multiplexers, respectively, having similar internal structures as those in PPS. Stages 2-4 of M2Clos are constructed by parallel switching planes; however, each plane is no longer formed by a basic  switch, but by a three-stage Clos Network to support large port count. Inside each Clos Network, the first stage is composed by k identical Input Modules. Each IM is an packet switch, with each output link connected to a Central Module. Thus, there are a total of m identical in second stage of the Close networks


SYSTEM REQUIREMENTS:
HARDWARE REQUIREMENTS:

•         System                 : Pentium IV 2.4 GHz.
•         Hard Disk            : 40 GB.
•         Floppy Drive       : 1.44 Mb.
•         Monitor                : 15 VGA Colour.
•         Mouse                  : Logitech.
•         Ram                     : 512 Mb.

SOFTWARE REQUIREMENTS:

•         Operating system                     :  Windows XP.
•         Coding Language           :  C#.NET

REFERENCE:
Lei Shi, Bin Liu, Changhua Sun, Zhengyu Yin, Laxmi N. Bhuyan, Fellow, IEEE, and H. Jonathan Chao, Load-Balancing Multipath Switching System with Flow Slice”, IEEE TRANSACTIONS ON COMPUTERS, VOL. 61, NO. 3, MARCH 2012.